Integrated I cache Way Predictor and Branch Target Bu er to Reduce Energy Consumption

In this paper we present a Branch Target Bu er BTB design for energy savings in set associative in struction caches We extend the functionality of a BTB by caching way predictions in addition to branch target addresses Way prediction and branch target prediction are done in parallel Instruction cache energy savings are achieved by accessing one cache way if the way pre diction for a fetch is available To increase the number of way predictions for higher energy savings we modify the BTB management policy to allocate entries for non branch instructions Fur thermore we propose to partition a BTB into ways for branch instructions and ways for non branch instruc tions to reduce the BTB energy as well We evaluate the e ectiveness of our BTB design and management policies with SPEC benchmarks The best BTB con guration shows a energy savings on average in a way set associative instruction cache and the performance degradation is only When the instruction cache energy and the BTB energy are considered together the average energy delay product reduction is